[Lehrstuhl Hotz]

[Bücher] [Diplomarbeiten] [Dissertationen] [Technische Berichte] [Zeitschriften] [Sonstiges]

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Zeitschriften und Konferenzbeiträge

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BibTeX-Einträge

117 references, last updated Thu May 11 15:23:51 2000

[Chadzelek and Hotz, 1999]
T. Chadzelek and G. Hotz. Analytic machines. Theoretical Computer Science, 219:151-167, 1999.

[Hotz and Gamkrelidze, 1998]
G. Hotz and A. Gamkrelidze. A note on the addition of m k-bit numbers. 1998. (Gzipped PostScript, 5 pages, 36822 bytes)
We give a method to construct a parallel adder of m k-bit numbers based on the school method of addition. As a result, we get a parallel adder with depth 1 log(n) + 12 and hardware cost k m. We apply our method to develop a parallel multiplier with asymptotical depth c log n and hardware cost n2

[Scholl, 1997]
C. Scholl. Functional decomposition with integrated test generation. In GI/ITG Workshop ``Testmethoden und Zuverlässigkeit von Schaltungen und Systemen'', 1997. (Gzipped PostScript, 4 pages, 56625 bytes)

[Scholl et al., 1997a]
C. Scholl, R. Drechsler, and B. Becker. Functional simulation using binary decision diagrams. In GI/ITG/GME Workshop ``Methoden des Entwurfs und der Verifikation digitaler Systeme'', 1997. (Gzipped PostScript, 10 pages, 77800 bytes)

[Scholl et al., 1997b]
C. Scholl, St. Melchior, G. Hotz, and P. Molitor. Minimizing ROBDD sizes of incompletely specified functions by exploiting strong symmetries. In Proceedings of the European Design and Test Conference 1997, March 1997. (Gzipped PostScript, 6 pages, 98429 bytes)

[Chadzelek et al., 1996]
Thomas Chadzelek, Jens Eckstein, and Elmar Schömer. Heuristic motion planning with many degrees of freedom. In 8th Canadian Conference on Computational Geometry, May 1996. (Gzipped PostScript, 6 pages, 52863 bytes)
We present a general heuristic approach to the geometric motion planning problem with the aim to quickly solve intuitively simple problems. It is based on a divide-and-conquer path search strategy which makes inquiries about feasible paths; to answer these, we develop an efficient collision detection scheme that handles translations and rotations of polyhedra to compute all times of collision. The whole algorithm can be easily implemented and universally applied and has been successfully tested in a program for assembly planning.

[Eckstein et al., 1996]
J. Eckstein, Th. Chadzelek, and E. Schömer. Heuristic motion planning with movable obstacles. In 8th Canadian Conference on Computational Geometry, 1996. (Gzipped PostScript, 6 pages, 247240 bytes)
We present a heuristic approach to geometric path planning with movable obstacle s. Treating movable obstacles as mobile robots leads to path planing problems with many degrees of freedom which are intractable. Our strategy avoids this computational complexity by decoupling the whole motion planning problem into a series of tractable problems, which are solved using kn own path planning algorithms. The individually computed solutions are then coordinated to a path plan. This method results in a powerful and practicable strategy for path planning wit h movable obstacles, which can be applied using a wide variety of known motion p lanning algorithms.

[Schieffer and Hotz, 1996]
Björn Schieffer and Günter Hotz. Fault diagnosis in heterogeneous complex systems. In Proceedings of the 3rd International Conference On Concurrent Engineering & Electronic Design Automation, CEE96, 1996. (Compressed PostScript, 6 pages, 104053 bytes)
In this paper a new approach for the diagnosis problem of complex heterogeneous systems is presented. It needs no linearization of the system and allows arbitrary influences between the subsystems, while this is not the case for many approaches in literature. As a domain example, ballast tanks in offshore plants are used.

[Schömer and Thiel, 1996]
E. Schömer and C. Thiel. Subquadratic algorithms for the general collision detection problem. In 12th European Workshop on Computational Geometry, pages 95-101, March 1996. (Gzipped PostScript, 7 pages, 65443 bytes)
We present the first subquadratic collision detection algorithm for simultaneously moving geometric objects which works in a fairly general setting. Geometric objects are regarded as rigid bodies in 3-space and are represented by unions of triangles (polyhedra) or unions of spheres (molecules). The motions of all objects are specified by polynomial functions which describe their position and orientation at any point in time. The general framework we develop for the solution of our specific problem is interesting of its own because it may be applicable for a wide range of other problems which require the solution of systems of polynomial (in)equalities.

[Schulz and Schoemer, 1996]
Frank Schulz and Elmar Schoemer. Self-organizing data structures with dependent accesses. In ICALP'96, pages 526-537, July 1996. (Gzipped PostScript, 12 pages, 58262 bytes)
We consider self-organizing data structures in the case where the sequence of accesses can be modeled by a first order Markov chain. For the simple-k- and batched-k--move-to-front schemes, explicit formulae for the expected search costs are derived and compared. We use a new approach that employs the technique of expanding a Markov chain. This approach generalizes the results of Gonnet/Munro/Suwanda. In order to analyze arbitrary memory-free move-forward heuristics for linear lists, we restrict our attention to a special access sequence, thereby reducing the state space of the chain governing the behaviour of the data structure. In the case of accesses with locality (inert transition behaviour), we find that the hierarchies of self-organizing data structures with respect to the expected search time are reversed, compared with independent accesses. Finally we look at self-organizing binary trees with the move-to-root rule and compare the expected search cost with the entropy of the Markov chain of accesses.

[Sparmann and Reddy, 1996]
U. Sparmann and S.M. Reddy. On the effectiveness of residue code checking for parallel two's complement multipliers. IEEE Transactions on VLSI Systems, 4(2), 1996. (Compressed PostScript, 17 pages, 172328 bytes)
The effectiveness of residue code checking for on-line error detection in parallel two's complement multipliers has up to now only been evaluated experimentally for few architectures. In this paper a formal analysis is given for most of the current multiplication schemes. Based on this analysis it is shown which check bases are appropriate, and how the original scheme has to be extended for complete error detection at the input registers and Booth recoding circuitry. In addition, we argue that the hardware overhead for checking can be reduced by approximately one half if a small latency in error detection is acceptable. Schemes for structuring the checking logic in order to guarantee it to be self-testing, and thus achieve the totally self-checking goal for the overall circuit, are also derived.

[Sparmann et al., 1996a]
U. Sparmann, H. Müller, and S.M. Reddy. Local transformations and robust dependent path delay faults. In Proceedings of the International Test Conference, 1996. (Compressed PostScript, 17 pages, 177126 bytes)
Local transformations are used in several synthesis approaches. During application of such transformations attention has to be paid to many important properties, e.g. area, speed, power consumption, and testability. In this paper we study relations between local transformations and delay fault testability. In delay testing it is not necessary to test every path in a circuit to ascertain correct timing behavior. For example, a set of robust dependent path delay faults need not be considered for testing if all paths that are not robust dependent are tested. We present sufficient conditions for local transformations which ensure that a test set for all non-robust-dependent paths in the original circuit is also a test set for all non-robust-dependent paths in the transformed circuit. These conditions are applied to some local transformations which are often used in logic synthesis and it is shown that they preserve testability. The impact of local transformations on robust dependent testability is demonstrated by experimental results performed on benchmark circuits.

[Sparmann et al., 1996b]
U. Sparmann, H. Müller, and S.M. Reddy. Minimal delay test sets for unate gate networks. In Proceedings of the 5th Asian Test Symposium, 1996. (Compressed PostScript, 10 pages, 134925 bytes)
We consider delay testing of a specific class of logic circuits, the so called `unate gate networks (UGNs)', which are of importance for the realization of dynamic CMOS logic and in the field of on-line error detection. It has been shown earlier, that UGNs can be tested completely for delay faults with `universal' test sets. This result even holds for designs which are not completely path delay testable, since the above test sets check the temporal correctness of a circuit by testing `path systems' instead of single paths. A universal test set only depends on the computed function and thus, is valid for any unate gate network implementation of this function. This universal test property has to be paid by an increase in test set size, since a design independent test set will in general be larger than a design dependent one. In this paper, we show how to tailor a universal test set to a specific design in order to reduce its size maximally without loosing test quality. Experimental results demonstrate that the resulting delay test sets are very compact, and large savings in test set size of up to 96.71 % can be achieved compared to the universal test set.

[Sparmann et al., 1996c]
U. Sparmann, H. Müller, and S.M. Reddy. Universal delay test sets for logic networks. to appear in: IEEE Transactions on VLSI Systems, 1996. (Preliminary version available as technical report 5-30-94, Department of ECE, University of Iowa, Iowa City, IA 52242, USA).

[Becker et al., 1995]
B. Becker, R. Hahn, J. Hartmann, and U. Sparmann. On the testability of iterative logic arrays. INTEGRATION, the VLSI Journal, 18:201-218, June 1995.

[Choi et al., 1995]
Joonsoo Choi, J"urgen Sellen, and Chee Yap. Precision-sensitive euclidean shortest path in 3-space. In Proceedings 11th Annual ACM Symposium on Computational Geometry, 1995. (Gzipped PostScript, 10 pages, 83916 bytes)

[Follert, 1995]
F. Follert. Maxmin location of an anchored ray in 3-space and related problems. In 7th Canadian Conference on Computational Geometry, pages ??--??, August 1995.
We consider the problem of locating a ray emanating from the origin of 3-space such as to maximize the minimum weighted Euclidean distance to a set of weighted obstacles (points, lines or line segments). We present algorithms based on the parametric search paradigm which run in O(n log 4 n) time in the case of point obstacles, and in O(n2 log 2 n) (O(n2 log 2 n 2 alpha (n))) time in the case of line (segment) obstacles. We also show that for practically interesting restricted settings of the line obstacle problem, subquadratic algorithms can be obtained. Furthermore we discuss some related problems.

[Follert et al., 1995]
F. Follert, E. Schömer, and J. Sellen. Subquadratic algorithms for the weighted maximin facility location problem. In 7th Canadian Conference on Computational Geometry, pages 1-6, August 1995. (Gzipped PostScript, 6 pages, 46055 bytes)
Let S be a set of n points in the plane, and let each point p of S have a positive weight w(p). We consider the problem of positioning a point x inside a compact region R subseteq R2 such that min { w(p)-1 cdot d( Bx ,p) ; p in S } is maximized. Based on the parametric search paradigm, we give the first subquadratic algorithms for this problem, with running time O(n log 4 n). Furthermore, we shall introduce the concept of `exact approximation' as the bit model counterpart to parametric search. Exploiting ideas from exact computation, we show that the considered problem can be solved in time O(L mu (L) n log n), where L denotes the maximal bit-size of input numbers, and mu (L) the complexity of multiplying two L-bit integers.

[Hartmann et al., 1995]
J. Hartmann, G. Hotz, R. Loos, R. Marzinkewitsch, J. Quapp, F. Weigel, and A. Weber. The ``optical formula recognition'' system for handprinted input. J. Symbolic Computation, 11:1-8, 10 March 1995. (Gzipped PostScript, 8 pages, 81671 bytes)

[Hotz et al., 1995]
Günter Hotz, Gero Vierke, and Börn Schieffer. Analytic machines. Technical Report TR95-025, Electronic Colloquium on Computational Complexity, 1995. (Compressed PostScript, 23 pages, 94493 bytes)
In this paper the R-machines defined by Blum, Shub and Smale are generalized by allowing infinite convergent computations. The description of real numbers is infinite. Therefore, considering arithmetic operations on real numbers should also imply infinite computations on analytic machines. We prove that R -computable functions are Q -analytic. We show that R-machines extended by finite sets of strong analytic operations are still Q -analytic. The halting problem of the analytic machines contains the stability problem of dynamic systems. It follows with well known methods that this problem is not analytical decidable. This is in a sense a stronger result as the numerical undecidable stability in the theory of Kolmogoroff, Arnold and Moser. Keywords: R -computability, stability, approximation

[Scholl and Molitor, 1995a]
C. Scholl and P. Molitor. Communication Based FPGA Synthesis for Multi-Output Boolean Functions. In ASP Design Automation Conf., pages 279-287, 1995. (Gzipped PostScript, 9 pages, 148251 bytes)

[Scholl and Molitor, 1995b]
C. Scholl and P. Molitor. Efficient ROBDD based computation of common decomposition functions of multioutput boolean functions. In G. Saucier and A. Mignotte, editors, Novel Approaches in Logic and Architecture Synthesis, pages 57-63. Chapman & Hall, 1995. (Gzipped PostScript, 7 pages, 64967 bytes)

[Schömer and Thiel, 1995]
E. Schömer and C. Thiel. Efficient collision detection for moving polyhedra. In 11th Annual Symposium on Computational Geometry, pages 51-60, June 1995. (Gzipped PostScript, 10 pages, 71927 bytes)
In this paper we consider the following problem: given two general polyhedra of complexity n, one of which is moving translationally or rotating about a fixed axis, determine the first collision (if any) between them. We present an algorithm with running time O(n8/5+ epsilon ) for the case of translational movements and running time O(n5/3+ epsilon ) for rotational movements, where epsilon is an arbitrary positive constant. This is the first known algorithm with sub-quadratic running time.

[Schömer et al., 1995]
E. Schömer, J. Sellen, and M. Welsch. Exact geometric collision detection. In 7th Canadian Conference on Computational Geometry, pages 211-216, August 1995. (Gzipped PostScript, 6 pages, 55491 bytes)
Exact computation is an important paradigm for the implementation of geometric algorithms. In this paper, we consider for the first time the practically important problem of collision detection under this aspect. The task is to decide whether a polyhedral object can perform a prescribed sequence of translations and rotations in the presence of stationary polyhedral obstacles. We present an exact decision method for this problem which is purely based on integer arithmetic. Our approach guarantees that the required binary length of intermediate numbers is bounded by 14L+22, where L denotes the maximal bit-size of any input value.

[Sellen, 1995a]
Jürgen Sellen. Direction weighted shortest path planning. In Proceedings IEEE Conference on Robotics and Automation, 1995. (Compressed PostScript, 6 pages, 65401 bytes)

[Sellen, 1995b]
Jürgen Sellen. Planning paths of minimal curvature. In Proceedings IEEE Conference on Robotics and Automation, 1995. (Compressed PostScript, 6 pages, 65401 bytes)

[Sparmann et al., 1995]
U. Sparmann, D. Luxenburger, K.T. Cheng, and S.M. Reddy. Fast identification of robust dependent path delay faults. In Proceedings of the 32nd Design Automation Conference, pages 119-125, 1995.

[Burch et al., 1994]
T. Burch, J. Hartmann, G. Hotz, M. Krallmann, U. Nikolaus, S.M. Reddy, and U. Sparmann. A hierarchical enviroment for interactive test engineering. In Proceedings of the International Test Conference 1994, pages 461-470, 1994.

[Choi et al., 1994]
Joonsoo Choi, Jürgen Sellen, and Chee Yap. Approximate euclidean shortest path in 3-space. In Proceedings 10th Annual ACM Symposium on Computational Geometry, 1994.

[Hotz and Pitsch, 1994a]
G. Hotz and G. Pitsch. Fast uniform analysis of coupled context free grammars. In Proceedings of the 21th International Colloquium on Automata, Languages and Programing, LNCS 820, pages 412-423. Springer Verlag, 1994.

[Hotz and Pitsch, 1994b]
G. Hotz and G. Pitsch. A representation theorem for coupled context free grammars. In Proceedings of the International Conference on Semigroups, Automata and Languages, pages 88-92, 1994.

[Molitor and Scholl, 1994]
P. Molitor and C. Scholl. Communication Based Multilevel Synthesis for Multi-Output Boolean Functions. In Great Lakes Symp. VLSI, pages 101-104, 1994. (Gzipped PostScript, 4 pages, 41350 bytes)

[Molitor et al., 1994]
P. Molitor, U. Sparmann, and D. Wagner. Two-layer assignment with pin preassignment is easier if power supply is already generated. In Proceeding of the 7th International Conference on VLSI Design, Calcutta, India, January 1994.

[Pitsch, 1994]
G. Pitsch. LL(k)-parsing of coupled context free grammars. Comput. Intelligence, 10, 1994.

[Schieffer, 1994]
Björn Schieffer. Fast compiler-driven hierarchical logic simulation. In Proceedings of the European Simulation Multiconference 94, pages 991-998, 1994. (Compressed PostScript, 8 pages, 103439 bytes)
Hierarchy can be used to make compiler-driven logic simulation available for very large circuits where the size of a flat simulation routine is too big. But due to many parameter evaluations, hierarchical simulators have an unacceptable runtime. In this paper, it is shown how to reach the performance of a flat simulator using hierarchical code but avoiding the expensive information transport with parameters.

[Scholl and P.Molitor, 1994]
C. Scholl and P.Molitor. Efficient ROBDD Based Computation of Common Decomposition Functions of Multi-Output Boolean Functions. In IFIP Workshop on Logic and Architecture Synthesis, Grenoble, pages 61-70, 1994. (Gzipped PostScript, 10 pages, 138193 bytes)

[Sparmann and Reddy, 1994a]
U. Sparmann and S.M. Reddy. On the effectiveness of residue code checking for parallel two's complement multipliers. In Proceedings of the 24th International Symposium on Fault-Tolerant Computing, 1994. (Compressed PostScript, 10 pages, 136623 bytes)
The effectiveness of residue code checking for on-line error detection in parallel two's complement multipliers has up to now only been evaluated experimentally for few architectures. In this paper a formal analysis is given for most of the current multiplication schemes. Based on this analysis it is shown which check bases are appropriate, and how the original scheme has to be extended for complete error detection at the input registers and Booth recoding circuitry. In addition, we argue that the hardware overhead for checking can be reduced by approximately one half if a small latency in error detection is acceptable. Schemes for structuring the checking logic in order to guarantee it to be self-testing, and thus achieve the totally self-checking goal for the overall circuit, are also derived.

[Sparmann and Reddy, 1994b]
U. Sparmann and S.M. Reddy. On the effectiveness of residue code checking for parallel two's complement multipliers. In Proceedings of the 24th International Symposium on Fault-Tolerant Computing, pages 219-228, 1994.

[Wu, 1994]
H. Wu. On n-column 0,1-matrices with all k-projections surjective. Acta Informatica, 1994. to appear.

[Becker et al., 1993]
B. Becker, R. Drechsler, and P. Molitor. On the implementation of an efficient performance driven generator for conditional-sum adders. In Proceedings of the 2nd European Design Automation Conference (EURODAC93), pages 402-407, September 1993.

[Hartmann, 1993]
J. Hartmann. On numerical weight optimization for random testing. In Proceedings of the joint EDAC-EUROASIC Conference, pages 223-230, 1993.

[Hartmann and Kemnitz, 1993]
J. Hartmann and G. Kemnitz. How to do weighted random testing for BIST? In Proceedings of the International Conference on CAD (ICCAD'93), 1993.

[Hotz, 1993]
G. Hotz. Search Trees and Search Graphs for Markov Sources. EIK Journal of Information Processing and Cybernetics, 29:283-292, 1993.

[Moeller and Mohnke, 1993]
D. Moeller and J. Mohnke. Detection of symmetry of boolean functions represented by robdds. In Proceedings of the International Conference on CAD (ICCAD'93), 1993.

[Mohnke and Malik, 1993]
J. Mohnke and S. Malik. Permutation and phase independent boolean comparison. In Proceedings of the joint EDAC-EUROASIC Conference, 1993.

[Molitor, 1993]
P. Molitor. A hierarchy preserving hierarchical bottom-up 2-layer wiring algorithm with respect to via minimization. INTEGRATION, the VLSI Journal, 15:73-95, 1993.

[Rollwage, 1993]
U. Rollwage. The complexity of mod-2 sum PLAs for symmetric functions. In IFIP WG 10.5 Workshop on Applications of the Reed-Muller Expansion in Circuit Design, 1993.

[Sparmann, 1993]
U. Sparmann. On the check base selection problem for fast adders. In Proceedings of the 11th IEEE VLSI Test Symposium, pages 62-65, 1993.

[Wu, 1993a]
H. Wu. On the Assignment Complexity of Uniform Trees. In Proceedings of the International Symposium on Symbolic and Algebraic Computation, pages 95-104, 1993.

[Wu, 1993b]
H. Wu. Synthesis of O( lg n) Testable Trees. In Proceedings of the 9th International Conference on Fundamentals of Computation Theory FCT93, pages 452-461, 1993.

[Zhu et al., 1993]
Bin Zhu, Xinyu Wu, Wenjun Zhuang, and Wai-Kai Chen. A New One-and-Half Layer Channel Routing Algorithm Based on Assigning Resources for CMOS Gate Array. IEEE Trans. CAD, Vol.12, No.2, pages 250-264, 1993.

[Becker and Drechsler, 1992]
B. Becker and R. Drechsler. A time optimal robust path-delay-fault self-testable adder. In Proceedings of the 1st European Design Automation Conference (EURODAC92), pages 376-381, September 1992.

[Becker and Hartmann, 1992]
B. Becker and J. Hartmann. Some remarks on the test complexity of iterative logic arrays. In Proceedings of the 17th International Symposium on Mathematical Foundations of Computer Science, 1992.

[Becker and Molitor, 1992]
B. Becker and P. Molitor. A performance driven generator for efficient testable adders. In Proceedings of the 1st European Design Automation Conference (EURODAC92), pages 370-375, September 1992.

[Drechsler et al., 1992]
R. Drechsler, B. Becker, and P. Molitor. A performance oriented generator for robust path-delay-fault testable adders. In Tagungsband des 4. ITG/GI-Workshops `Testmethoden und Zuverlässigkeit von Schaltungen und Systemen', 1992.

[Drefenstedt and Walle, 1992]
R. Drefenstedt and Th. Walle. Parametric ASIC--design by CADIC. In Proceedings of the 3rd European Design Automation Conference (EDAC92), 1992.

[Hartmann et al., 1992a]
Joachim Hartmann, Björn Schieffer, and Uwe Sparmann. Cell oriented fault simulation. In Proceedings of the European Simulation Multiconference 92, pages 424-429, 1992. (Compressed PostScript, 6 pages, 53972 bytes)
Currently, in most fault simulators physical defects have to be modeled as stuck-at faults in networks of primitive gates such as AND, NAND etc. Especially for complex gates this modeling technique is rather inexact. In this paper, a fault simulation approach supporting a more powerful and variable fault model is presented. Specification of faults is done in a cell oriented manner. To achieve maximum flexibility, the set of basic cells and their failure modes are not coded into the algorithm but can be specified by the user in a library. For the special case of compiler driven fault simulation it is shown that this increased flexibility does not degrade the performance of the simulator but, in contrast, results in a considerable speed-up (up to factor 35).

[Hartmann et al., 1992b]
Joachim Hartmann, Björn Schieffer, and Uwe Sparmann. Zur effizienten Testerzeugung für sequentielle Fehlermodelle. In Tagungsband des 4. ITG/GI-Workshops `Testmethoden und Zuverlässigkeit von Schaltungen und Systemen', 1992. (Compressed PostScript, 4 pages, 30018 bytes)
Es wird ein allgemeiner Ansatz der Modellierung sequentieller Fehler auf seine Anwendbarkeit für Fehlersimulation und Testmustergenerierung untersucht. Zur Steigerung der Effizienz wird das Konzept der blind homing sequence vorgestellt.

[Kaufmann et al., 1992]
M. Kaufmann, P. Molitor, and W. Vogelgesang. Performance driven k-layer wiring. In Proceedings of the 9th Annual Symposium on Theoretical Aspects of Computer Science (STACS92), LNCS 577, pages 489-500, February 1992.

[Marzinkewitsch and others, 1992]
R. Marzinkewitsch et al. Fast preprocessing of handprinted symbols for pattern recognition with neural networks. In Tagungsband der Göttinger Neurobiologenkonferenz, 1992.

[Sellen, 1992]
J. Sellen. About the topological structure of configuration spaces. In Proceedings of the Conference on Artificial Intelligence and Symbolic Mathematical Computations, August 1992.

[Sparmann, 1992]
U. Sparmann. Derivation of high quality tests for large heterogeneous circuits: Floating-point operations (extended abstract). In Proceedings of the 3rd European Conference on Design Automation 92, pages 355-360, 1992.

[Wu, 1992]
H. Wu. On tests of uniform tree circuits. In Proceedings of the CONPAR'92 VAPP V Conference, pages 527-538, September 1992.

[Wu and Sparmann, 1992]
H. Wu and U. Sparmann. On the Assignment Complexity of VLSI Tree systems. In Proceedings of the ISCIS VII Conference, pages 97-104, November 1992.

[Becker and Sparmann, 1991a]
B. Becker and U. Sparmann. Computations over finite monoids and their test complexity. Theoretical Computer Science, pages 225-250, 1991.

[Becker and Sparmann, 1991b]
B. Becker and U. Sparmann. A uniform test approach for RCC-Adders. Fundamenta Informaticae, Annales Societatis, Mathematicae Polonae, pages 185-219, 1991.

[Becker et al., 1991]
B. Becker, R. Hahn, R. Krieger, and U. Sparmann. Structure based methods for parallel pattern fault simulation in combinational circuits. In Proceedings of the 2nd European Design Automation Conference (EDAC91), 1991.

[Hartmann, 1991]
J. Hartmann. The random testability of the n-input AND gate. In Proceedings of the 8th Annual Symposium on Theoretical Aspects of Computer Science, pages 488-498, February 1991.

[Hartmann et al., 1991]
Joachim Hartmann, Björn Schieffer, and Uwe Sparmann. COFS - a cell oriented fault simulator. In Tagungsband des 3. ITG/GI-Workshops `Testmethoden und Zuverlässigkeit von Schaltungen und Systemen', 1991. (Compressed PostScript, 14 pages, 71255 bytes)
Currently, in most fault simulators physical defects have to be modeled as stuck-at faults in networks of primitive gates such as AND, NAND, etc. On the other hand, the inadequacy of the stuck-at fault model for today's technologies has been pointed out by many authors. In this paper, a compiler driven fault simulator is presented which handles arbitrary combinational faults. The set of basic cells and their fault models are not coded into the algorithm but can be specified by the user in a library. It is shown that this increased flexibility, which is obtained by cell instead of line oriented fault injection, does not degrade the performance of the simulator but, in contrast, results in a considerable speed-up (up to factor 40).

[Hotz et al., 1991]
G. Hotz, P. Molitor, and W. Zimmer. On the construction of very large integer multipliers. In Proceedings of EURO ASIC 91, pages 266-269, May 1991.

[Kaufmann and Molitor, 1991]
M. Kaufmann and P. Molitor. Minimal stretching of a layout to ensure 2-layer wirability. INTEGRATION, the VLSI Journal, 12:339-352, December 1991.

[Kolla and Serf, 1991]
R. Kolla and B. Serf. The virtual feedback problem in hierarchical representations of combinational circuits. Acta Informatica, 28:463-476, 1991.

[Marzinkewitsch, 1991]
R. Marzinkewitsch. Operating computer algebra systems by handprinted input. In Proceedings of ISSAC 91, 1991.

[Molitor, 1991]
P. Molitor. A survey on wiring. EIK Journal of Information Processing and Cybernetics, EIK 27(1):3-19, 1991.

[Pitsch and Schömer, 1991]
G. Pitsch and E. Schömer. Optimal Parallel Recognition of Bracket Languages on Hypercubes. In Proceedings of the 8th Annual Symposium on Theoretical Aspects of Computer Science (STACS91), pages 434-443, February 1991.

[Wu, 1991]
H. Wu. On the construction of l timesn boolean matrices with all l timesk submatrices having 2k distinct row vectors. In Proceedings of the 2nd European Design Automation Conference (EDAC91), 1991.

[Becker and Hartmann, 1990a]
B. Becker and J. Hartmann. Optimal-time multipliers and c-testability. EIK Journal of Information Processing and Cybernetics, pages 547-561, 1990. Has also appeared in Proceedings of the 2nd Annual Symposium on Parallel Algorithms and Architectures (SPAA90).

[Becker and Hartmann, 1990b]
B. Becker and J. Hartmann. Optimal-time multipliers and C-testability. In Proceedings of the 2nd Annual Symposium on Parallel Algorithms and Architectures, pages 146-154, 1990.

[Becker et al., 1990]
B. Becker, Th. Burch, G. Hotz, D. Kiel, R. Kolla, P. Molitor, H. G. Osthof, G. Pitsch, and U. Sparmann. A graphical system for hierarchical specifications and checkups of VLSI circuits. In Proceedings of the 1st European Design Automation Conference (EDAC90), pages 174-179, 1990.

[Burch and Vogelgesang, 1990]
Th. Burch and W. Vogelgesang. A graphical system for recursive circuit specifications and fast transformations to EDIF. In Proceedings of the 4th European EDIF Forum, October 1990. 6 pages.

[Hartmann, 1990]
J. Hartmann. Analyse zweier Techniken zur Erhöhung der Zufallstestbarkeit. In Tagungsband des 2. ITG/GI-Workshops `Testmethoden und Zuverlässigkeit von Schaltungen und Systemen', 1990. 6 Seiten.

[Hinsberger and Kolla, 1990]
U. Hinsberger and R. Kolla. Cell based performance optimization of combinational circuits. In Proceedings of the 1st European Design Automation Conference (EDAC90), pages 594-599, 1990.

[Kolla, 1990a]
R. Kolla. A dynamic programming approach to the power supply net sizing problem. In Proceedings of the 1st European Design Automation Conference (EDAC90), pages 600-604, 1990.

[Kolla, 1990b]
R. Kolla. Minimum area sizing of power supply nets in VLSI circuits. EIK Journal of Information Processing and Cybernetics, 11-12:585-605, 1990.

[Molitor, 1990]
P. Molitor. Constrained via minimization for systolic arrays. IEEE Transactions on Computer Aided Design, CAD-9(5):537-542, May 1990.

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U. Sparmann and W. Weber. Zur Erstellung qualitativ hochwertiger Tests für gro\3e kombinatorische Schaltkreise. In Tagungsband des ITG/GI-Workshops `Testmethoden und Zuverlässigkeit von Schaltungen und Systemen', 1990. 7 Seiten.

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B. Becker and R. Kolla. On the construction of optimal time adders. Fundamenta Informaticae, Annales Societatis, Mathematicae Polonae, XII:205-220, 1989.

[Becker and Sparmann, 1989]
B. Becker and U. Sparmann. Computations over finite monoids and their test complexity (Extended Abstract). In 19th International Symposium on Fault-Tolerant Computing, pages 299-306, 1989.

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J. Hartmann. Über probabilistisches und deterministisches Testen. In Tagungsband des 1. ITG/GI-Workshops `Testmethoden und Zuverlässigkeit von Schaltungen und Systemen', 1989. 4 Seiten.

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R. Kolla and P. Molitor. A note on hierarchical layer assignment. INTEGRATION, the VLSI Journal, 7:213-230, 1989.

[Becker, 1988]
B. Becker. Efficient testing of optimal-time adders. IEEE Transactions on Computers, C-37:1113-1121, 1988.

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B. Becker and H.U. Simon. How robust is the n--cube ? Information and Computation, 77(2):162-178, 1988.

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B. Becker and U. Sparmann. Regular structures and testing: RCC-adders. In Proceedings of the 3rd Aegean Workshop on Computing, pages 288-300, 1988.

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A. Böttcher, G. Lawitzky, and H. U. Simon. Worstcase-analysis of heuristics for the local microcode optimization problem. Operations Research Letters, 7(3):127-130, 1988.

[Molitor, 1988]
P. Molitor. Free net algebras in VLSI-theory. Fundamenta Informaticae, Annales Societatis, Mathematicae Polonae, XI:117-142, June 1988.

[Simon, 1988a]
H.U. Simon. Approximative Lösungen des Mehrprozessor-Scheduling-Problems. Siemens Forsch.-- u. Entwickl.--Ber., 17(1):18-24, 1988.

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H.U. Simon. A continuous bound on the performance of critical-path schedules. EIK Journal of Information Processing and Cybernetics, 24(4/5):171-189, 1988.

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U. Sparmann. Design and test of a pattern matching circuit. EIK Journal of Information Processing and Cybernetics, 24:329-338, 1988.

[Becker, 1987]
B. Becker. An easily testable optimal time VLSI-multiplier. Acta Informatica, 24:363-380, 1987.

[Becker and Hotz, 1987]
B. Becker and G. Hotz. On the optimal layout of planar graphs with fixed boundary. SIAM Journal on Computing, 16(5), October 1987.

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B. Becker and H.G. Osthof. Layouts with wires of balanced length. Information and Computation, 73(1):45-58, April 1987.

[Becker and Soukup, 1987]
B. Becker and H. Soukup. CMOS stuck-open self-test for an optimal VLSI-multiplier. The EuroMicro Journal, Microprocessing and Microprogramming, 20:153-157, 1987.

[Becker et al., 1987a]
B. Becker, G. Hotz, R. Kolla, P. Molitor, and H.G. Osthof. CADIC - Ein System zum hierarchischen Entwurf integrierter Schaltungen. In Tagungsband des 3-ten E.I.S.-Workshops, pages 235-245, 1987.

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B. Becker, G. Hotz, R. Kolla, P. Molitor, and H.G. Osthof. Hierarchical design based on a calculus of nets. In Proceedings of the 24th ACM/IEEE Design Automation Conference (DAC87), pages 649-653, June 1987.

[Molitor, 1987]
P. Molitor. On the contact minimization problem. In Proceedings of the 4th Annual Symposium on Theoretical Aspects of Computer Science (STACS87), pages 420-431, February 1987.

[Becker and Simon, 1986]
B. Becker and H.U. Simon. How robust is the n-cube? In Proceedings of the 27th FOCS, pages 283-291, October 1986.

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B. Becker, G. Hotz, R. Kolla, and P. Molitor. Ein logisch topologischer Kalkül zur Konstruktion von integrierten Schaltkreisen. INFORMATIK, FORSCHUNG & ENTWICKLUNG, 1(1,2):38-47,72-82, 1986.

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G. Hotz, R. Kolla, and P. Molitor. On network algebras and recursive functions. In Proceedings of the 3rd International Workshop on Graph Grammars and Their Applications to Computer Science, LNCS 291, pages 250-261. Springer Verlag, 1986.

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B. Becker and H.G. Osthof. Layouts with wires of balanced length. In Proceedings of the 2nd Annual Symposium on Theoretical Aspects of Computer Science (STACS85), pages 21-31, January 1985.

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P. Molitor. Layer assignment by simulated annealing. The EuroMicro Journal, Microprocessing and Microprogramming, 16:345-350, 1985.

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U. Becker-Groh and G. Hotz. Ein Planaritätstest für planar-konvexe Grapheinbettungen mit linearer Komplexität. Beiträge zur Algebra und Geometrie, 18:191-200, 1984.

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G. Hotz. Eindeutigkeit und Mehrdeutigkeit formaler Sprachen. EIK Journal of Information Processing and Cybernetics, 2:235-246, 1966.

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G. Hotz. Eine Algebraisierung des Syntheseproblems für Schaltkreise. EIK Journal of Information Processing and Cybernetics, 1:185-205,209-231, 1965.

[Hotz, 1962]
G. Hotz. Einbettung von Streckenkomplexen in die Ebene. Mathematische Annalen, 167:214-223, 1962.

[Hotz, 1961]
G. Hotz. Zur Reduktionstheorie der booleschen Algebra. In Colloquium über Schaltkreis- und Schaltwerk-Theorie (1960). mbox Birkhäuser Verlag, 1961.

[Sellena]
Jürgen Sellen. Lower bounds for geometrical and physical problems. In SIAM Journal on Computing. to appear. (Compressed PostScript, 23 pages, 119011 bytes)

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Jürgen Sellen. On the topological structure of configuration spaces. In Annals of Mathematics and Artificial Intelligence. to appear. (Compressed PostScript, 22 pages, 93029 bytes)

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Thomas Chadzelek , 07/98